Much like houses are given street addresses, each location in a computer's memory where data may be stored is given a memory address. And just like a traveler can locate a friend's house by using a street address, a computer processor is able to access specific memory by using its memory address. Each memory address is a different pattern of bits; that is, ones or zeros. The number of bits used in a memory address is always the same for a given processor. For example, one commonly used central processing unit (“CPU”) microarchitecture includes 44 address bits, and so is able to address up to 244 bytes, or 16 terabytes (“TB”) of memory; that is, approximately 17.59 trillion different bytes. Similarly, another common CPU design includes 46 physical address bits, and so is able to address up to 246 bytes, or 64 TB of memory; that is, about 70.37 trillion byes. Because the number of address bits is fixed in the processor design, a computer processor is only able to address a finite maximum memory address space.
As technology has improved, high performance computing (“HPC”) systems have been developed, and over time these systems have increased their processing capacities. HPC systems include a number of modular computing nodes that have processors and memory. In some cases, the total memory of the system is more memory than can be addressed by its processors. When this occurs, a choice must be made regarding which memory receive an address (and thereby be accessible), and which memory should not receive an address (and thereby be inaccessible). Most prior HPC systems have not often experienced this problem because most modern processors have a large number of addressing bits. However, for those systems that have reached the limits of the addressing capabilities of their installed processors, their system operators have had to make a manual choice of which memory to address. Implementing this choice often required a great deal of expertise and understanding of performance compromises and other tradeoffs that could or should be made between various components in the HPC system, and a great deal of manual trial and error to find the right balance of capabilities.